Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks including block RAM (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
A user design may implement a multiprocessing system in a PLD that includes multiple dedicated processors. A user design may also implement a multiprocessing system by implementing soft processors in the programmable logic and interconnect resources of the PLD. An example user design may implement a multiprocessing system in a PLD using a dedicated processor and a soft processor that is a state machine specifically designed to implement a particular function of the user design.
To perform the function of the user design, the processors may need to exchange data. It may be time consuming and expensive to design the protocols for exchanging data between the processors of a multiprocessing system. The exchange of data between the processors may limit the performance of the multiprocessing system.
The present invention may address one or more of the above issues.